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RISC-V processor verification made easy
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Overview
ImperasDV is a front-end design verification solution for custom processors based on the RISC-V Instruction Set Architecture (ISA). It includes reference models, verification components, functional coverage, test suites, and a debugger.
Because RISC-V is an open standard ISA, it allows any developer the freedom to design and extend a custom processor, while remaining compatible with the growing ecosystem of supporting tools and software. RISC-V processor verification requires a solution that matches the configurable and extendable nature of the ISA. It must work with users’ existing environments and should make use of open standard interfaces such as the RISC-V Verification Interface (RVVI) to enable efficiency and reuse. RISC-V verification solutions should support industry best practices such as constrained-random stimulus and functional coverage. It is vital the solution addresses the processor-specific challenge of verifying DUT behavior in response to asynchronous events, as these events are a frequent source of bugs.
ImperasDV is a solution that meets all these requirements. It uses the ImperasFPM (Fast Processor Model) as a reference model for design verification. The model can be configured and extended to match the processor under test, including custom features. ImperasDV can be used in SystemVerilog/UVM testbenches, or with any language that has a C interface. It uses the RVVI-TRACE interface to connect to the processor under test and provides continuous comparison and checking of architectural state. It handles random occurrences of asynchronous events using a novel pipeline synchronization technology. ImperasDV also provides a machine-generated functional coverage model of each extension in the RISC-V ISA.
